Results stemming from this call must be well documented and widely disseminated. Precise documentation, user manuals as well as video tutorials must be made available. Selected consortia must develop teaching materials and courses with open resources and examples based on the developed/improved open-source EDA tools, accessible to academic institutions across the EU and suitable for self-study by individuals. To this end, collaboration with initiatives such as EUROPRACTICE is encouraged.

Consortia must actively engage with the Platform Coordination Team of the Chips Act’s Design Platform to integrate their tools into the platform’s design flows. Proposals must outline a clear strategy for engaging with relevant foundries to secure access to the required PDKs.

Proposals should clearly specify the applicable OSI-approved open-source license for all results. Proposals must also include a sustainability plan for results following the end of the project.

The three selected consortia must collaborate in their technical work where relevant. Joint communication and dissemination efforts are encouraged.

The expected outcomes for each of the aforementioned streams are the following:

1. Digital SoC design

The overall ambition of this stream is to ensure a comprehensive and stable digital design flow in more mainstream nodes (65-28nm). Improvement of tools in more mature nodes is also within scope of this stream. To this end a baseline for the quality of results currently achievable with current state-of-the-art open-source tools needs to be determined.

ii. Analogue and mixed-signal design

The overall ambition of this stream is the development of a full analogue/mixed-signal design flow. The emphasis should extend beyond improving existing tools to include the adoption of innovative approaches and new paradigms.

iii.Productivity, interoperability, and verification

The overarching aim of this stream is to enhance productivity by adopting innovative design approaches and ensuring seamless data exchange between tools. This will be complemented by the development of robust verification processes that accommodate diverse methodologies and effectively tackle the increasing complexity of modern chip design.